The present invention relates to a decoding apparatus and method, and more particularly, to a decoding apparatus and method which is capable of suppressing the decoding deterioration in transfer data when a transfer-data modulation method is changed.
In Japan, the Radio Regulatory Council submitted a report in which digital broadcasting service by the use of a broadcasting satellite (hereinafter called a BS) will be implemented by a BS4 satellite, which will be launched in the future. Data to be transferred includes main information formed of video signals and audio signals, a transfer method indicating a data encoding rate and a modulation method, a TMCC (transmission multiplexing configuration control) signal in which transport stream (TS) information in data is encoded, and fixed information formed of special-pattern data used for stopping propagation of a transfer-data error.
The main information is encoded and transferred by a QPSK (quadrature phase shift keying) modulation method at an encoding rate R of 1/2, 2/3, 3/4, 5/6, or 7/8, or at a TC8PSK (trelliscoded-coded 8 phase shift keying) method at an encoding rate R of 2/3. The TMCC signal and the fixed information are transferred via a BPSK (binary phase shift keying) signal encoded at an encoding rate of 1/2 (R=1/2). An encoding method and a decoding method used when basic modulation methods (TC8PSK, BPSK, and QPSK) are employed in a time-division manner in the above broadcasting method will be described below by referring to FIG. 5.
An information generator 1 converts the main information, the TMCC signal, and the fixed information, which are binary, to serial data. A serial-to-parallel converter 2 outputs serial data as it is when the serial data is modulated by the BPSK or QPSK modulation method, and converts serial data to two-bit parallel data and outputs it when the serial data is modulated by the TC8PSK modulation method.
An encoder 3 convolutionally encodes input data and outputs it. A mapping circuit 4 assigns input data to a BPSK, QPSK, or TC8PSK signal point according to the respective modulation methods, and outputs an I signal and a Q signal to a transmission line 5.
A decoder 6 receives the I signal and the Q signal; decodes it to one-bit data when the convolutionally encoded signals have been modulated by the BPSK or QPSK modulation method, and decodes it to two-bit data when the convolutionally encoded signals have been modulated by the TC8PSK modulation method; and outputs the data. A parallel-to-serial converter 7 outputs an input signal as it is when the input signal has been modulated by the BPSK or QPSK modulation method, and converts the two-bit parallel data to serial data and outputs it when the input signal has been modulated by the TC8PSK modulation method. A TMCC controller 8 controls the information generator 1 to the mapping circuit 4 by the use of the TMCC signal.
The information generator 1 will be further described by referring to FIG. 6. An information output circuit 21 sends the fixed information (TAB1 and TAB2 shown in FIG. 6) to an input terminal 11-1 and an input terminal 11-3 of a switching circuit 22, respectively; sends the TMCC signal (TMCC shown in FIG. 6) to an input terminal 11-2; and sends the main information (main information 0 to main information 47 shown in FIG. 6) to an input terminal 12-0 to an input terminal 12-47, respectively. The switching circuit 22 switches between the input terminals 11-1 to 11-3 and the input terminals 12-0 to 12-47 by a signal switcher 13 in a time-division manner, generates each serial data (TAB1, TMCC, TAB2, and main information 0 to main information 47), and outputs it to the serial-to-parallel converter 2.
FIG. 7 shows a frame structure of the data switched by the signal switcher 13 of the switching circuit 22. One superframe is formed of eight frames, a frame 0 to a frame 7. The frame 0 is formed of the fixed information TAB1, TMCC, the fixed information TAB2, and the main information 0 to the main information 47. A frame 1 to the frame 7 are formed in the similar way to the frame 0 except that the fixed information TAB2 in the frame 0 is replaced with fixed information TAB3. The fixed information TAB1, the fixed information TAB2, and the fixed information TAB3 have special patterns of 0x1B95, 0xA340, and 0x5CBF, respectively.
As the encoder 3, a trellis encoder which performs convolutional encoding will be described below by referring to FIG. 8. When a signal input from the serial-to-parallel converter 2 has been modulated by a modulation method other than the TC8PSK modulation method, an input bit (one bit) is input. When the input signal has been modulated by the TC8PSK modulation method, two bits, an input bit and a parallel bit, are input. In any of the modulation methods, the trellis encoder encodes an input bit at an encoding rate R of 1/2 and outputs an output bit 2 and an output bit 3. The parallel bit is not encoded and output as it is as an output bit 1. In other words, the trellis encoder encodes a two-bit input signal (input bit and parallel bit) at an encoding rate R of 2/3 to generate three bits.
The input bit is input to a delay circuit 31 formed of a register, an exclusive-OR circuit 33, and an exclusive-OR circuit 34. The delay circuit 31 delays the input input bit by a one-time-unit period, and outputs to a delay circuit 32 and the exclusive-OR circuit 33. The delay circuit 32 formed of a register delays the input input bit by a one-time-unit period and outputs to the exclusive-OR circuit 33 and the exclusive-OR circuit 34. The exclusive-OR circuit 33 calculates the exclusive OR of the input bit, the signal input from the delay circuit 31, and the signal input from the delay circuit 32, every one-time-unit period, and outputs the result as the output bit 2. The exclusive-OR circuit 34 calculates the exclusive OR of the input bit and the signal input from the delay circuit 32, every one-time-unit period, and outputs the result as the output bit 3.
The mapping circuit 4 maps the signal input from the encoder 3 onto signal points shown in FIG. 9 according to the signal modulation method. FIG. 9(A) shows signal-point arrangement for the signals (fixed information TAB1, fixed information TAB2, and TMCC signal) modulated by the BPSK modulation method. FIG. 9(B) shows signal-point arrangement for the signals (main information 0 to main information 47) modulated by the TC8PSK modulation method. These signal points indicate encoded transfer data which the mapping circuit 4 outputs. Two signal points (for example, a signal point (100) and a signal point (000)) positioned symmetrically against the center of the circle shown in FIG. 9(B) form a branch of the encoded transfer data. In a branch, one of the signal points has an MSB (most significant bit) of 1 (for example, the MSB of the signal point (100)) and the other has an MSB of 0 (for example, the MSB of the signal point (000)), and the signal points have the same bits (for example, the lower two bits, 00, of the signal point (100) and the signal point (000)) except the MSBs.
A Detailed structure of the decoder 6 will be described below by referring to FIG. 10. A branch-metric (hereinafter called BM) generator 41 calculates the square Euclidean distances of the received signals (I, Q) (corresponding to the I coordinate and the Q coordinate in the signal-point arrangement shown in FIG. 9) and the signal points (for example, the signal point (000) and the signal point (111) shown in FIG. 9(B)) of each branch, respectively, and outputs as four BM signals (BM00, BM01, BM10, and BM11). The BM generator 41 also outputs parallel-bit (hereinafter called PB) information (PB00, PB01, PB10, and PB11) selected correspondingly to each branch.
When a receiving point R (xe2x88x920.173, 0.984) is received as a received signal modulated by the TC8PSK modulation method as shown in FIG. 11, for example, the square Euclidean distances (to say simply, the lengths of solid lines in FIG. 11) between the receiving point R, and the signal points (000) and (100) are calculated, and whichever shorter (in the case of FIG. 11, the distance between the receiving point R and the signal point (100) since the square Euclidean distance between the receiving point R and the signal point (100) is shorter than that between the receiving point R and the signal point (000)) is set in the BM signal BM00. The MSB (=1) of the signal point (100) used in the calculation of the BM signal BM00 is assigned to the PB information PB00 corresponding to the BM signal BM00. In the same way, the square Euclidean distances (the lengths of dotted lines in FIG. 11) between the receiving point R, and signal points (001) and (101) are calculated. In this case, the distance between the receiving point R and the signal point (001) is set to the BM signal BM01, and a value 0 (which is the MSB of the signal point (001)) is assigned to PB information PB01. BM signals BM10 and BM11, and PB information PB10 and PB11 are calculated in the same way. In other words, the BM generator 41 calculates branch metrics from the receiving point R corresponding to the received signal, and outputs BM signals and PB information used for decoding the signal points (transfer data) output from the mapping circuit 4.
When the receiving point R1 (xe2x88x920.173, 0.984) of a signal modulated by the BPSK modulation method is received at a time t=t1 and a receiving point R2 (xe2x88x920.173, xe2x88x920.984) is received at a time t=t1+1, a BM signal BM00 is calculated by the following expression as shown in FIG. 12.
BM00=bm0(t1)+bm0(t1+1)
In this expression, bm0(t1) indicates the square Euclidean distance (=(+1xe2x88x92(xe2x88x920.173))2) between the I component (=xe2x88x920.173) of the receiving point R1 and the I component (=+1) of the signal point (0), and bm0(t1+1) indicates the square Euclidean distance (=(+1xe2x88x92(xe2x88x920.173))2) between the I component (=xe2x88x920.173) of the receiving point R2 and the I component (=+1) of the signal point (0). A BM signal BM01 is calculated by the following expression in the same way.
BM01=bm0(t1)+bm1(t1+1)
In this expression, bm0(t1) indicates the same value as that described above and therefore a description thereof is omitted, and bm1(t1+1) indicates the square Euclidean distance (=(xe2x88x921xe2x88x92(xe2x88x920.173))2) between the I component (=xe2x88x920.173) of the receiving point R2 and the I component (=xe2x88x921) of the signal point (1). The other BM signals are calculated by the following expressions in the same way.
BM10 bm1(t1)+bm0(t1+1)
BM11 bm1(t1)+bm1(t1+1)
Since a parallel bit has no meaning (since a parallel bit is not input to the encoder 3 for a signal modulated by the BPSK modulation method and therefore an indefinite value is output from the encoder, it has no meaning as data) in the BPSK modulation method, any values are assigned to PB information PB00 to PB11.
FIG. 13 shows the state transitions of the basic codes (which correspond to the bits excluding the MSB of signal points used for calculating a branch metric from a receiving point, and are 00, 01, 10, and 11) of a received signal. In other words, basic codes at a before-transition state and an after-transition state shown in FIG. 13 indicate the internal states of the encoder 3 (trellis encoder). A state 00 indicates that the delay circuit 31 and the delay circuit 32 shown in FIG. 8 hold a value 0 and a value 0, respectively, a state 01 indicates that they hold a value 0 and a value 1, respectively, a state 10 indicates that they hold a value 1 and a value 0, respectively, and a state 11 indicates that they hold a value 1 and a value 1, respectively. An arrow from each state before a transition to each state after the transition corresponds to a state transition. When a value 0 is input at the state 00 (corresponding to the values of the delay circuit 31 and the delay circuit 32), for-example, a value 00 (corresponding to the output bit 2 and the output bit 3) is output and the state is changed to a state 00 (corresponding to the values of the delay circuit 31 and the delay circuit 32). Therefore, a symbol 0/00 shown at I/O indicates an input of 0 and an output of 00. The other arrows and I/O""s have the corresponding meanings in the same way.
The above state transition can be described in the following way by the operations of the encoder 3 shown in FIG. 8. When an input bit of 0 is input to the encoder 3 while the register of the delay circuit 31 has a value of 0 and the register of the delay circuit 32 has a value of 0 (state 00), the encoder 3 outputs an output bit 2 of 0 and an output bit 3 of 0 (output 00) as the calculation result. After the calculation, the register of the delay circuit 31 has a value of 0 and the register of the delay circuit 32 has a value of 0 (transition to state 00). In the same way, when a value of 1 is input at the state 00, a value of 11 is output and the state is changed to the state 10. When a value of 0 is input at the state 10, a value of 10 is output and the state is changed to the state 01. When a value of 1 is input at the state 10, a value of 01 is output and the state is changed to the state 11. The other state transitions can be calculated in the same way.
The values (corresponding to the values (SM00, SM0, SM10, and SM11) which registers 54A to 54D having resets shown in FIG. 14 have) of the state metrics (hereinafter called SMs) corresponding to state transitions from each state are calculated. A sicnal output when a state is changed correspond to a BM signal and PB information. Specifically, the output 00 corresponds to the BM signal BM00 and the PB information PB00, the output 01 corresponds to the BM signal BM01 and the PB information PB01, the output 10 corresponds to the BM signal BM10 and the PB information PB10, and the output 11 corresponds to the BM signal BM11 and the PB information PB11.
An ACS (add, compare, and select) circuit 42 receives the four pieces of PB information (PB00, PB01, PB10, and PB11) and the four BM signals (BM00, BM01, BM10, and BM11), and outputs PB information and path memory selection information (pb00, se100), (pb01, se101), (pb10, se110), and (pb11, se111). Details of the ACS circuit 42 will be described below by referring to a block diagram shown in FIG. 14.
An adder 51A adds the BM signal BM00 (BM value obtained when the state 00 is changed to the state 00) sent from the BM generator 41 to the value SM00 (the state metric value (hereinafter called SM value) at the state 00 before the transition) of the register 54A having a reset to calculate the likelihood (SM value) obtained when the state 00 is changed to the state 00. An adder 52A adds the BM signal BM11 (BM value obtained when the state 01 is changed to the state 00) sent from the BM generator 41 to the value SM01 (the SM value at the state 01 before the transition) of the register 54B having a reset to calculate the likelihood (SM value) obtained when the state 01 is changed to the state 00. At the initial state of decoding, the registers 54A to 54D having resets are reset to zero by reset signals output from a reset circuit (not shown).
After the transition, a comparator 53A compares the SM value obtained when the state 00 was changed to the state 00 with the SM value obtained when the state 01 was changed to the state 00, and selects whichever has a larger-likelihood path (SM value). When the SM value (the output of the adder 51A) obtained when the state 00 was changed to the state 00 is equal to or smaller than that the SM value (the output of the adder 52A) obtained when the state 01 was changed to the state 00, the comparator 53A outputs the smaller SM value (the output of the adder 51A) to the register 54A having a reset, and outputs to a path memory 43 a value of 0 as path-memory (hereinafter called PM) selection information se100 and PB00 corresponding to the selected SM value as the PB information pb00. Conversely, when the SM value (the output of the adder 51A) obtained when the state 00 was changed to the state 00 is larger that the SM value (the output of the adder 52A) obtained when the state 01 was changed to the state 00, the comparator 53A outputs the smaller SM value (the output of the adder 52A) to the register 54A having a reset, and outputs to the path memory 43 a value of 1 as the PM selection information se100 and PB11 corresponding to the selected SM value as the PB information pb00. The register 54A having a reset stores the SM value selected by the comparator 53A as a state metric at the state 00.
An adder 51B, an adder 52B, a comparator 53B, and the register 54B perform the same calculation as the adder 51A, the adder 52A, the comparator 53A, and the register 54A. The SM value (path likelihood) obtained when the state 10 or the state 11 is changed to the state 01 is calculated, and the PM selection information SE101 and the PB information pb01 are output to the path memory 43. As for a transition to the state 10 and that to the state 11, the same operation is performed. The BM generator 41 and the ACS circuit 42 perform the above processing every time a received signal (for example, the receiving point R shown in FIG. 11) is received.
The path memory 43 selects the maximum-likelihood path by the use of values (pb00, 0), (pb01, 0), (pb10, 1), and (pb11, 1) in which values 0, 0, 1, and 1 are combined with the PM selection information se100, se101, se11, and se111 and the PB information pb00, pb01, pb10, and pb11. Details of the path memory 43 will be described below by referring to a block diagram shown in FIG. 15. The relationship between a register and a selector in each column (for example, registers 63A to 63D and selectors 64A to 64D serving as register-output destinations) in the path memory 43 corresponds to the state transition shown in FIG. 13. Among registers in the first rows corresponding to the state 00, a register 61A in the first column stores the value (pb00, 0) corresponding to the PB information pb00 at the state 00 sent from the ACS circuit 42. A selector 62A selecting a path at the state 00 selects either the value (pb00, 0) sent from the first-column register 61A corresponding to the state 00 or the value (pb01, 0) sent from the first-column register 61B among registers in the second row corresponding to the state 01, according to the PM selection information se100; outputs it to a register 63A in the second column corresponding to the state 00; and stores in it.
The first-column register 61A stores a combination of the PB information pb00 (for example, PB00) obtained when the state is changed to the state 00 and input from the ACS circuit 42, and a value 0. The first-column register 61B in the second row stores a combination of the PB information pb01 (for example, PB10) obtained when the state is changed to the state 01 and input from the ACS circuit 42, and a value 0. The value of the register 61A and that of the register 61B are input to the selector 62A. The selector 62A corresponding to the state 00 outputs the value (pb00 (for example, the value of PB00, 0), 0) input from the register 61A to the second-column register 63A according to the PM selection information se100 (for example, a value 0 which specifies the selection from the state 00) input from the ACS circuit 42.
In the path memory 43, selections and transitions of combined values are performed according to the PM selection information for all columns (receiving-point count) and all states (state 00 to state 11), as described above. Finally, one of the combined value (the value stored in a register 76A) of the state 00 to the combined value (the value stored in a register 76D) of the state 11 is selected according to information xe2x80x9csmminxe2x80x9d indicating the minimum state-metric value as the combined value of the maximum-likelihood state in a selector 77. The selected combined value is output.
Path selection processing is applied to data input at a point of time by the number (the number of received signals) of the columns of the path memory 43. This means that data input at a point of time is affected by data input thereafter, is delayed by the number (the number of received signals) of the columns of the path memory 43, and is output.
When the modulation method is changed from the BPSK method to the PC8PSK method at a time xe2x80x9ct,xe2x80x9d for example, data conforming to the BPSK modulation method is input at a time (txe2x88x921) and a branch metric is calculated. Then, in the ACS circuit 42, path-selection information is calculated according to the result of the branch-metric calculation. Path-memory selection processing is performed in the path memory 43.
Until the output corresponding to the data input at the time (txe2x88x921) is obtained, however, the data of the BPSK modulation method is affected by data which is modulated by the TC8PSK modulation method and input after the time xe2x80x9ct.xe2x80x9d Since the branch metric corresponding to data modulated by the TC8PSK modulation method has a relatively low reliability of likelihood than the branch metric corresponding to the data modulated by the BPSK modulation method, the reliability of the path-selection information corresponding to the data modulated by the TC8PSK modulation method is also lower. As a result, although transfer is performed by the BPSK modulation method to increase reliability, since the transfer method is changed to the TC8PSK modulation method, an error characteristic deteriorates at a point where the transfer method is changed.
The present invention has been made in consideration of the above situation. Accordingly, it is an object of the present invention to detect the position of fixed information in transferred data convolutionally encoded, to determine whether a code transition state is terminated, and to control the value of a state metric, such that the deterioration of an error characteristic in decoding the transfer data is suppressed when the transfer-data modulation method is changed.
In order to solve the above problem, in the present invention, a decoding apparatus for decoding transfer data in which main information and fixed information are convolutionally encoded includes: a generation means for generating the branch metric corresponding to the transition state of the code of the convolutionally encoded transfer data; a selection means for calculating a state metric according to the branch metric and for selecting the path of the code; a detection means for detecting the position of the fixed information in the transfer data; a control means for controlling the value of the state metric of the fixed information correspondingly to a detection result obtained by the detection means; and a storage means for storing the selection state of the path of the code according to the selection of the path.
Further, a decoding method for decoding transfer data in which main information and fixed information are convolutionally encoded includes: a generation step of generating the branch metric corresponding to the transition state of the code of the convolutionally encoded transfer data; a selection step of calculating a state metric according to the branch metric and of selecting the path of the code; a detection step of detecting the position of the fixed information in the transfer data; a control step of controlling the value of the state metric of the fixed information correspondingly to a detection result obtained in the detection step; and a storage step of storing the selection state of the path of the code according to the selection of the path.